1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly relates to a semiconductor device including a plurality of semiconductor chips electrically connected by through silicon vias.
2. Description of Related Art
A memory capacity required in semiconductor memory devices such as DRAM (Dynamic Random Access Memory) is increasing every year. In recent years, there has been proposed a method to meet this requirement. In this method, a plurality of memory chips are stacked and electrically connected via through silicon vias arranged on a silicon substrate (see Japanese Patent Application Laid-open No. 2007-158237).
Specifically, in a semiconductor memory device in which an interface chip having front end units such as interface circuits incorporated thereon and a core chip having back end units such as memory cores incorporated thereon are stacked, because read data that is read in parallel from the memory cores is supplied as it is to the interface chip without performing serial conversion, a large number of through silicon vias (approximately 4000 units in some cases) are required. However, the entire chip becomes defective when even one of the through silicon vias becomes defective, and if a plurality of the chips are stacked, all the chips become defective. Thus, to prevent the entire chip from becoming defective due to a defective through silicon via, auxiliary through silicon vias are sometimes provided in such semiconductor memory devices.
In the semiconductor device disclosed in Japanese Patent Application Laid-open No. 2007-158237, one auxiliary through silicon via is allocated to a group of through silicon vias constituted by a plurality of through silicon vias (for example, eight through silicon vias).
However, when a defective through silicon via is simply replaced with an auxiliary through silicon via, an unignorable difference in wiring lengths can occur between signal paths before and after replacement of the through silicon vias depending on a location of the defective through silicon via. That is, for example, when a defect occurs to a through silicon via that is located near the auxiliary through silicon via, a difference in wiring lengths between signal paths before and after replacement of the through silicon vias is very small. However, when a defect occurs to a through silicon via that is located away from the auxiliary through silicon via, a signal path after replacement of the through silicon vias is longer by an amount equivalent to detouring of a signal path up to the auxiliary through silicon via. Such a difference in the wiring lengths can generate skew in a signal input into and/or output from the through silicon via. The skew can degrade the signal quality.
This problem is not limited to semiconductor memory devices such as DRAMs, but can occur to all semiconductor devices that include a plurality of semiconductor chips that are electrically connected to each other via through silicon vias.